As semiconductor devices continue to decrease in size, the elements that make up these devices, such as channel lengths, intervals between active areas, via holes, metal studs, contact sizes, and the widths of metal interconnection also decrease. Due to the miniaturization of semiconductor devices including capacitors, such as a dynamic random access memory (DRAM), methods for forming self aligned contacts (SACs) are being used due to lack of a misalignment margin in a photolithography process. For example, a buried contact pad and a direct contact pad may be formed between word lines of a DRAM using a method for forming a SAC, and a buried contact plug may be formed between bit lines of a DRAM using the same method for forming a SAC. Thus, the lower electrode of the capacitor may be formed so that it is in contact with the buried contact plug and connected to the impurity region within the active area through the buried contact pad and the buried contact plug.
Typically, the direct contact pad, the buried contact pad, and the buried contact plug are formed using a doped polycrystalline silicon layer. Doped polycrystalline silicon layers have superior filling ability and stability in the presence of heat which makes them a desirable material for the elements of a semiconductor device. Furthermore, the doped polycrystalline silicon layer has an advantage over other materials in that a contact resistance of the semiconductor device may be reduced due to activation of a dopant by a high temperature annealing process. However, the high temperature annealing process may have negative effects on other elements of the device.
For example, a buried contact pad and a direct contact pad that are in direct contact with an n+ type impurity region of a semiconductor substrate may be provided. If the buried contact pad is formed using a doped polycrystalline silicon layer and the annealing process is used to activate the dopant, impurities of the doped polycrystalline silicon layer may be diffused within the semiconductor substrate, thus possibly causing the electrical characteristics of a transistor to deteriorate.
By way of further example, a p+ type impurity region within the semiconductor device that is not in direct contact with metal interconnection on the semiconductor substrate may be provided in order to overcome an increased height difference between the impurity region and the metal interconnection. Instead, after a metal stud connected to the p+ type impurity region is formed, the metal stud is in contact with the metal interconnection instead of the p+ type impurity region. The metal stud may be formed during a middle step when the bit lines of the cell area are formed.
In this case, a titanium silicide (Ti-silicide) layer is typically formed on the lower portion or the upper portion of the metal stud as a barrier metal layer for an ohmic contact. A high temperature annealing process may be accompanied by a step of forming the buried contact plug using the doped polycrystalline silicon layer, a step of activating the polycrystalline silicon layer dopant, and a step of forming a dielectric layer forming the capacitor, which are performed after the metal stud is formed. Impurities of the p+ type impurity region, for example, boron, may be diffused into the Ti-silicide layer by this high temperature annealing process such that a titanium-boron compound is formed which may result in an increased contact resistance.